FW82801EB Intel, FW82801EB Datasheet - Page 206

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.19.4.4
5.19.4.5
5.19.4.6
5.19.4.7
206
Table 94. Address Field
Table 95. Endpoint Field
Cyclic Redundancy Check (CRC)
Address Fields
Function endpoints are addressed using the function address field and the endpoint field.
Address Field
The function address (ADDR) field specifies the function, via its address, that is either the source
or destination of a data packet, depending on the value of the token PID. As shown in
total of 128 addresses are specified as ADDR[6:0]. The ADDR field is specified for IN, SETUP,
and OUT tokens.
Endpoint Field
An additional four-bit endpoint (ENDP) field, shown in
of functions in which more than one sub-channel is required. Endpoint numbers are function
specific. The endpoint field is defined for IN, SETUP, and OUT token PIDs only.
Frame Number Field
The frame number field is an 11-bit field that is incremented by the host on a per frame basis. The
frame number field rolls over upon reaching its maximum value of x7FF, and is sent only for SOF
tokens at the start of each frame.
Data Field
The data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. Data bits
within each byte are shifted out LSB first.
CRC is used to protect the all non-PID fields in token and data packets. In this context, these fields
are considered to be protected fields. The PID is not included in the CRC check of a packet
containing CRC. All CRCs are generated over their respective fields in the transmitter before bit
stuffing is performed. Similarly, CRCs are decoded in the receiver after stuffed bits have been
removed. Token and data packet CRCs provide 100% coverage for all single and double bit errors.
A failed CRC is considered to indicate that one or more of the protected fields is corrupted and
causes the receiver to ignore those fields, and, in most cases, the entire packet.
Bit
Bit
0
1
2
3
0
1
2
3
Data Sent
Data Sent
ADDR 0
ADDR 1
ADDR 2
ADDR 3
ENDP 0
ENDP 1
ENDP 2
ENDP 3
Bit
4
5
6
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Table
Data Sent
ADDR 4
ADDR 5
ADDR 6
95, permits more flexible addressing
Table
94, a