FW82801EB Intel, FW82801EB Datasheet - Page 209

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.19.5.5
5.19.6
5.19.6.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
USB Interrupts
Transaction Based Interrupts
Handshake Responses
IN Transaction
A function may respond to an IN transaction with a STALL or NAK. If the token received was
corrupted, the function issues no response. If the function can transmit data, it issues the data
packet. The ICH5, as the USB host, can return only one type of handshake on an IN transaction, an
ACK. If it receives a corrupted data, or cannot accept data due to a condition such as an internal
buffer overrun, it discards the data and issues no response.
OUT Transaction
A function may respond to an OUT transaction with a STALL, ACK, or NAK. If the transaction
contained corrupted data, it issues no response.
SETUP Transaction
Setup defines a special type of host to function data transaction which permits the host to initialize
an endpoint’s synchronization bits to those of the host. Upon receiving a Setup transaction, a
function must accept the data. Setup transactions cannot be STALLed or NAKed and the receiving
function must accept the Setup transfer’s data. If a non-control endpoint receives a SETUP PID, it
must ignore the transaction and return no response.
There are two general groups of USB interrupt sources, those resulting from execution of
transactions in the schedule, and those resulting from an ICH5 operation error. All
transaction-based sources can be masked by software through the ICH5’s Interrupt Enable register.
Additionally, individual transfer descriptors can be marked to generate an interrupt on completion.
When the ICH5 drives an interrupt for USB, it internally drives the PIRQA# pin for USB
function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC# pin for USB
function #2, until all sources of the interrupt are cleared. In order to accommodate some operating
systems, the Interrupt Pin register must contain a different value for each function of this new
multi-function device.
These interrupts are not signaled until after the status for the last complete transaction in the frame
has been written back to host memory. This guarantees that software can safely process through
(Frame List Current Index -1) when it is servicing an interrupt.
CRC Error / Time-Out
A CRC/Time-Out error occurs when a packet transmitted from the ICH5 to a USB device or a
packet transmitted from a USB device to the ICH5 generates a CRC error. The ICH5 is informed of
this event by a time-out from the USB device or by the ICH5’s CRC checker generating an error on
reception of the packet. Additionally, a USB bus time-out occurs when USB devices do not
respond to a transaction phase within 19-bit times of an EOP. Either of these conditions causes the
C_ERR field of the TD to decrement.
Functional Description
209