FW82801EB Intel, FW82801EB Datasheet - Page 215

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.20
5.20.1
5.20.1.1
5.20.1.2
Intel
®
Table 101. UHCI vs. EHCI
82801EB ICH5 / 82801ER ICH5R Datasheet
USB EHCI Host Controller (D29:F7)
The ICH5 contains an Enhanced Host Controller Interface (EHCI) compliant host controller which
supports up to eight USB 2.0 high speed compliant root ports. USB 2.0 allows data transfers up to
480 Mbps using the same pins as the eight USB full speed/low speed ports. The ICH5 contains
port-routing logic that determines whether a USB port is controlled by one of the UHCI controllers
or by the EHCI controller. USB 2.0 based Debug Port is also implemented in the ICH5.
A summary of the key architectural differences between the USB UHCI host controllers and the
EHCI host controller are shown in
EHC Initialization
The following descriptions step through the expected ICH5 Enhanced Host Controller (EHC)
initialization sequence in chronological order, beginning with a complete power cycle in which the
suspend well and core well have been off.
Power On
The suspend well is a “deeper” power plane than the core well, which means that the suspend well
is always functional when the core well is functional but the core well may not be functional when
the suspend well is. Therefore, the suspend well reset pin (RSMRST#) deasserts before the core
well reset pin (PWROK) rises.
BIOS Initialization
BIOS performs a number of platform customization steps after the core well has powered up.
Contact your Intel Field Representative for additional ICH5 BIOS information.
Accessible by
Memory Data Structure
Differential Signaling Voltage
Ports per Controller
1. The suspend well reset deasserts, leaving all registers and logic in the suspend well in the
2. The core well reset deasserts, leaving all registers and logic in the core well in the default state.
default state. However, it is not possible to read any registers until after the core well reset
deasserts. Note that normally the suspend well reset only occurs when a system is unplugged.
In other words, suspend well resets are not easily achieved by software or the end-user. This
step will typically not occur immediately before the remaining steps.
The EHC configuration space is accessible at this point. Note that the core well reset can (and
typically does) occur without the suspend well reset asserting. This means that all of the
Configure Flag and Port Status and Control bits (and any other suspend-well logic) may be in
any valid state at this time.
Parameter
I/O space
3.3 V
2
Single linked list
Table
USB UHCI
101.
400 mV
Memory Space
Separated in to Periodic and Asynchronous lists
8
USB EHCI
Functional Description
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