FW82801EB Intel, FW82801EB Datasheet - Page 220

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.20.6
5.20.6.1
220
USB 2.0 Interrupts and Error Conditions
Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus,
Revision 1.0 goes into detail on the EHC interrupts and the error conditions that cause them. All
error conditions that the EHC detects can be reported through the EHCI Interrupt status bits. Only
ICH5-specific interrupt and error-reporting behavior is documented in this section. The EHCI
Interrupts Section must be read first, followed by this section of the datasheet to fully comprehend
the EHC interrupt and error-reporting functionality.
Aborts on USB 2.0-Initiated Memory Reads
If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following
actions are taken when this occurs:
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Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer Error can
never occur on the ICH5.
Master Abort and Target Abort responses from hub interface on EHC-initiated read packets
will be treated as Fatal Host Errors. The EHC halts when these conditions are encountered.
The ICH5 may assert the interrupts which are based on the interrupt threshold as soon as the
status for the last complete transaction in the interrupt interval has been posted in the internal
write buffers. The requirement in the Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (that the status is written to memory) is met internally, even
though the write may not be seen on the hub interface before the interrupt is asserted.
Since the ICH5 supports the 1024-element Frame List size, the Frame List Rollover interrupt
occurs every 1024 milliseconds.
The ICH5 delivers interrupts using PIRQH#.
The ICH5 does not modify the CERR count on an Interrupt IN when the “Do Complete-Split”
execution criteria are not met.
For complete-split transactions in the Periodic list, the “Missed Microframe” bit does not get
set on a control-structure-fetch that fails the late-start test. If subsequent accesses to that
control structure do not fail the late-start test, then the “Missed Microframe” bit will get set
and written back.
The Host System Error status bit is set
The DMA engines are halted after completing up to one more transaction on the USB interface
If enabled (by the Host System Error Enable), then an interrupt is generated
If the status is Master Abort, then the Received Master Abort bit in configuration space is set
If the status is Target Abort, then the Received Target Abort bit in configuration space is set
If enabled (by the SERR Enable bit in the function’s configuration space), then the Signaled
System Error bit in configuration bit is set.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet