FW82801EB Intel, FW82801EB Datasheet - Page 226

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.20.10
5.20.10.1
226
USB 2.0 Based Debug Port
The ICH5 supports the elimination of the legacy COM ports by providing the ability for new
debugger software to interact with devices on a USB 2.0 port.
High-level restrictions and features are:
The Debug port facilitates OS and device driver debug. It allows the software to communicate with
an external console using a USB 2.0 connection. Because the interface to this link does not go
through the normal USB 2.0 stack, it allows communication with the external console during cases
where the OS is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is
being debugged. Specific features of this implementation of a debug port are:
There are two operational modes for the USB debug port:
Theory of Operation
1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host
2. Mode 2 is when the host controller is running (i.e., host controller’s Run/Stop# bit is 1). In
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Must be operational before USB 2.0 drivers are loaded.
Must work even when the port is disabled.
Must work even though non-configured port is default-routed to the classic controller. Note
that the Debug Port can not be used to debug an issue that requires a full speed/low speed
device on Port #0 using the UHCI drivers.
Must allow normal system USB 2.0 traffic in a system that may only have one USB port.
Debug Port device (DPD) must be high-speed capable and connect to a high-speed port on
ICH5 systems.
Debug Port FIFO must always make forward progress (a bad status on USB is simply
presented back to software).
The Debug Port FIFO is only given one USB access per microframe.
Only works with an external USB 2.0 debug device (console)
Implemented for a specific port on the host controller
Operational anytime the port is not suspended AND the host controller is in D0 power state.
Capability is interrupted when port is driving USB RESET
controller driver. In Mode 1, the Debug Port controller is required to generate a “keepalive”
packets less than 2 ms apart to keep the attached debug device from suspending. The keepalive
packet should be a standalone 32-bit SYNC field.
Mode 2, the normal transmission of SOF packets will keep the debug device from suspending.
Intel
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82801EB ICH5 / 82801ER ICH5R Datasheet