FW82801EB Intel, FW82801EB Datasheet - Page 240

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
240
Table 114. I
Note: This command is supported independent of the setting of the I2C_EN bit. The I
I
This command allows the ICH5 to perform block reads to certain I
E
However, this does not allow access to devices using the I
bytes after the address. Typically these data bytes correspond to an offset (address) within the serial
memory chips.
with the PEC_EN bit set produces undefined results. Software must force both the PEC_EN and
AAC bit to 0 when running this command.
For I
I/O register, offset 04h) needs to be 0.
The format that is used for the new command is shown in
The ICH5 will continue reading data from the peripheral until the NAK is received.
2
27:21
37:30
46:39
18:11
2
2
C Read
8:2
Bit
PROMs. The SMBus Block Read supports the 7-bit addressing mode only.
C Block Read
10
19
20
28
29
38
47
1
9
–
–
–
–
2
C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB
Start
Slave Address — 7 bits
Write
Acknowledge from slave
Send DATA1 register
Acknowledge from slave
Repeated Start
Slave Address — 7 bits
Read
Acknowledge from slave
Data byte 1 from slave — 8 bits
Acknowledge
Data byte 2 from slave — 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data byte N from slave — 8 bits
NOT Acknowledge
Stop
Description
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
2
Table
C “Combined Format” that has data
114.
2
C devices, such as serial
2
C Read command