FW82801EB Intel, FW82801EB Datasheet - Page 246

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

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Functional Description
5.21.7.1
246
Table 119. Slave Write Cycle Format
Table 120. Slave Write Registers
Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH5 SMBus Slave I/F. The
“Command” field (bits 11
indicate the value that should be written to that register.
The Write Cycle format is shown in
registers.
NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data
18:11
27:20
Bits
8:2
10
19
28
29
1
9
Register
9–FFh
1–3
6–7
byte registers until they have been read by the system processor. The ICH5 overwrites the old value
with any new value received. A race condition is possible where the new value is being written to the
register just at the time it is being read. ICH5 will not attempt to cover this race condition
(i.e., unpredictable results in this case).
0
4
5
8
Start Condition
Slave Address — 7 bits
Write
ACK
Command
ACK
Register Data
ACK
Stop
Description
Command Register. See
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Frequency Straps will be written on bits 3:0. Bits 7:4 should be 0, but will be ignored.
Reserved
:
18) indicate which register is being accessed. The Data field (bits 20
External Microcontroller
External Microcontroller
External Microcontroller
ICH5
External Microcontroller
ICH5
External Microcontroller
ICH5
External Microcontroller
Table
Table 121
Driven By
119.
Table 120
Intel
below for legal values written to this register.
®
Function
82801EB ICH5 / 82801ER ICH5R Datasheet
has the values associated with the
Must match value in Receive Slave Address
register
Always 0
This field indicates which register will be
accessed.
See
See
Table 120
Table 120
for the register definitions
for the register definitions
Comment
:
27)

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