FW82801EB Intel, FW82801EB Datasheet - Page 250

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.21.7.2.1
5.21.7.3
250
Table 124. Host Notify Format
Note: An external microcontroller must not attempt to access the ICH5’s SMBus Slave logic until at least
Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any necessary
Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit
Write bit sequence. When the ICH5 detects that the address matches the value in the Receive Slave
Address register, it will assume that the protocol is always followed and ignore the Write bit (bit 9)
and signal an Acknowledge during bit 10 (See
–
matches the ICH5’s Slave Address, the ICH5 will still grab the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start
sequence beginning at bit 20 (See
Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with
the Slave Read cycle.
1 second after both RTCRST# and RSMRST# are deasserted (high).
Format of Host Notify Command
The ICH5 tracks and responds to the standard Host Notify command as specified in the System
Management Bus (SMBus) Specification, Version 2.0. The host address for this command is fixed
to 0001000b. If the ICH5 already has data for a previously-received host notify command which
has not been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit), then
it will NACK following the host address byte of the protocol. This allows the host to communicate
non-acceptance to the master and retain the host notify address and data values for the previous
cycle until host software completely services the interrupt.
reads of the address and data registers.
Table 124
Address
17:11
27:20
36:29
Bit
8:2
10
18
19
28
37
38
1
9
–
ACK (or NACK)
Data Byte Low — 8 bits
Start
SMB Host Address — 7 bits
Write
Device Address – 7 bits
Unused — Always 0
ACK
ACK
Data Byte High — 8 bits
ACK
Stop
Read occurs (which is illegal for SMBus Read or Write protocol), and the address
shows the Host Notify format.
Description
Table
External Master
External Master
External Master
External Master
External Master
ICH5
External Master
ICH5
External Master
ICH5
External Master
Intel
Driven By
122). Once again, if the Address matches the ICH5’s
®
ICH5
Table 119
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Always 0001_000
Always 0
ICH5 NACKs if HOST_NOTIFY_STS is 1
Indicates the address of the master; loaded into
the Notify Device Address Register
7-bit-only address; this bit is inserted to complete
the byte
Loaded into the Notify Data Low Byte Register
Loaded into the Notify Data High Byte Register
and
Table
122). In other words, if a Start
Comment
–
Address
–
Read
–
Address
–