FW82801EB Intel, FW82801EB Datasheet - Page 253

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.22.1
5.22.2
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCI Power Management
This Power Management section applies for all AC ’97 controller functions. After a power
management event is detected, the AC ’97 controller wakes the host system. The following
sections describe these events and the AC ’97 controller power states.
Device Power States
The AC ’97 controller supports D0 and D3 PCI Power Management states. The following are notes
regarding the AC ’97 controller implementation of the Device States:
AC-Link Overview
The ICH5 is an AC ’97 2.3 controller that communicates with companion codecs via a digital serial
link called the AC-link. All digital audio/modem streams and command/status information is
communicated over the AC-link.
The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data
streams, as well as control register accesses, employing a time division multiplexed (TDM)
scheme. The AC-link architecture provides for data transfer through individual frames transmitted
in a serial fashion. Each frame is divided into 12 outgoing and 12 incoming data streams, or slots.
The architecture of the ICH5 AC-link allows a maximum of three codecs to be connected.
Figure 24
10. Once the interrupt status bits are set, they will cause PIRQB# if their respective enable bits
1. The AC ’97 controller hardware does not inherently consume any more power when it is in the
2. In the D0 state, all implemented AC ’97 controller features are enabled.
3. In D3 state, accesses to the AC ’97 controller memory-mapped or I/O range results in master
4. In D3 state, the AC ’97 controller interrupt must never assert for any reason. The internal
5. When the Device Power State field is written from D3
6. AC97 STS bit is set only when the audio or modem resume events were detected and their
7. GPIO Status change interrupt no longer has a direct path to the AC97 STS bit. This causes a
8. Resume events on AC_SDIN[2:0] cause resume interrupt status bits to be set only if their
9. Edge detect logic prevents the interrupts from being asserted in case the AC97 controller is
D0 state than it does in D3 state. However, software can halt the DMA engine prior to entering
these low power states such that the maximum power consumption is reduced.
abort.
PME# signal is used to signal wake events, etc.
See
respective PME enable bits were set.
wake up event only if the modem controller was in D3
respective controllers are not in D3.
switched from D3 to D0 after a wake event.
were set. One of the audio or the modem drivers will handle the interrupt.
Section 16.1
shows a three codec topology of the AC-link for the ICH5.
for general rules on the effects of this reset.
HOT
to D0, an internal reset is generated.
Functional Description
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