FW82801EB Intel, FW82801EB Datasheet - Page 255

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Figure 27. AC-Link Protocol
82801EB ICH5 / 82801ER ICH5R Datasheet
ICH5 core well outputs may be used as strapping options for the ICH5, sampled during system
reset. These signals may have weak pullups/pulldowns; however, this will not interfere with link
operation. ICH5 inputs integrate weak pulldowns to prevent floating traces when a secondary and/
or tertiary codec is not attached. When the Shut Off bit in the control register is set, all buffers will
be turned off and the pins will be held in a steady state, based on these pullups/pulldowns.
AC_BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides the
necessary clocking to support the twelve 20-bit time slots. AC-link serial data is transitioned on
each rising edge of AC_BIT_CLK. The receiver of AC-link data samples each serial bit on the
falling edge of AC_BIT_CLK.
If AC_BIT_CLK makes no transitions for four consecutive PCI clocks, the ICH5 assumes the
primary codec is not present or not working. It sets bit 28 of the Global Status Register
(I/O offset 30h). All accesses to codec registers with this bit set will return data of FFh to prevent
system hangs.
Synchronization of all AC-link data transactions is signaled by the AC ’97 controller via the
AC_SYNC signal, as shown in
AC-link, which the AC ’97 controller then qualifies with the AC_SYNC signal to construct data
frames. AC_SYNC, fixed at 48 kHz, is derived by dividing down AC_BIT_CLK. AC_SYNC
remains high for a total duration of 16 AC_BIT_CLKs at the beginning of each frame. The portion
of the frame where AC_SYNC is high is defined as the tag phase. The remainder of the frame
where AC_SYNC is low is defined as the data phase. Each data bit is sampled on the falling edge
of AC_BIT_CLK.
The ICH5 has three AC_SDIN pins allowing a single, dual, or triple codec configuration. When
multiple codecs are connected, the primary, secondary, and tertiary codecs can be connected to any
AC_SDIN line. The ICH5 does not distinguish between codecs on its AC_SDIN[2:0] pins,
however the registers do distinguish between AC_SDIN0, AC_SDIN1, and AC_SDIN2 for wake
events, etc. If using a Modem Codec it is recommended to connect it to AC_SDIN1.
See your Platform Design Guide for a matrix of valid codec configurations. The ICH5 does not
support optional test modes as outlined in the AC ’97 Specification, Version 2.3.
BIT_CLK
SDIN
SYNC
End of previous
Audio Frame
Codec
Ready
12.288 MHz
slot(1)
("1" = time slot contains valid PCM
Tag Phase
slot(2)
81.4 nS
Time Slot "Valid"
Figure
slot(12)
Bits
"0"
25. The primary codec drives the serial bit clock onto the
"0"
"0"
19
Slot 1
0
(48 KHz)
20.8uS
19
Slot 2
Data Phase
0
19
Functional Description
Slot 3
0
19
Slot 12
0
255