FW82801EB Intel, FW82801EB Datasheet - Page 265

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.22.7
5.22.8
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Hardware Assist to Determine AC_SDIN Used Per Codec
Software Mapping of AC_SDIN to DMA Engine
The transition of AC_RST# to the deasserted state only occurs under driver control. In the S1sleep
state, the state of the AC_RST# signal is controlled by the AC ’97 Cold Reset# bit (bit 1) in the
Global Control register. AC_RST# is asserted (low) by the ICH5 under the following conditions:
Hardware never deasserts AC_RST# (i.e., never deasserts the Cold Reset# bit) automatically. Only
software can deassert the Cold Reset# bit and, hence, the AC_RST# signal. This bit, while it
resides in the core well, remains cleared upon return from S3/S4/S5 sleep states. The AC_RST#
pin remains actively driven from the resume well as indicated.
Software first performs a read to one of the audio codecs. The read request goes out on
AC_SDOUT. Since under our micro-architecture only one read can be performed at a time on the
link, eventually the read data will come back in on one of the AC_SDIN[2:0] lines.
The codec does this by indicating that status data is valid in its TAG, then echoes the read address
in slot 1 followed by the read data in slot 2.
The new function of the ICH5 hardware is to notice which AC_SDIN line contains the read return
data, and to set new bits in the new register indicating which AC_SDIN line the register read data
returned on. If it returned on AC_SDIN0, bits [1:0] contain the value 00. If it returned on
AC_SDIN1, the bits contain the value 01, etc.
ICH5 hardware can set these bits every time register read data is returned from a function 5 read.
No special command is necessary to cause the bits to be set. The new driver/BIOS software reads
the bits from this register when it cares to, and can ignore it otherwise. When software is
attempting to establish the codec-to-AC_SDIN mapping, it will single feed the read request and not
pipeline to ensure it gets the right mapping, we cannot ensure the serialization of the access.
Once software has performed the register read to determine codec-to-AC_SDIN mapping, it will
then either set bits [5:4] or [7:6] in the SDATA_IN MAP register to map this codec to the DMA
engine. After it maps the audio codecs, it sets the “SE” (steer enable) bit, which now lets the
hardware know to no longer OR the AC_SDIN lines, and to use the mappings in the register to
steer the appropriate AC_SDIN line to the correct DMA engines.
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RSMRST# (system reset, including the a reset of the resume well and PCIRST#)
Mechanical power up (causes PCIRST#)
Write to CF9h hard reset (causes PCIRST#)
Transition to S3/S4/S5 sleep states (causes PCIRST#)
Write to AC ’97 Cold Reset# bit in the Global Control Register.
Functional Description
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