FW82801EB Intel, FW82801EB Datasheet - Page 269

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

6.2
6.3
6.3.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCI Configuration Map
Each PCI function on the ICH5 has a set of PCI configuration registers. The register address map
tables for these register sets are included at the beginning of the chapter for the particular function.
Refer to
Configuration Space registers are accessed through configuration cycles on the PCI bus by the
Host bridge using configuration mechanism #1 detailed in the PCI Local Bus Specification,
Revision 2.3.
Some of the PCI registers contain reserved bits. Software must deal correctly with fields that are
reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on
reserved bits being any particular value. On writes, software must ensure that the values of
reserved bit positions are preserved. That is, the values of reserved bit positions must first be read,
merged with the new values for other bit positions and then written back. Note the software does
not need to perform read, merge, write operation for the configuration address register.
In addition to reserved bits within a register, the configuration space contains reserved locations.
Software should not write to reserved PCI configuration locations in the device-specific region
(above address offset 3Fh).
I/O Map
The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be moved, but
in some cases can be disabled. Variable ranges can be moved and can also be disabled.
Fixed I/O Address Ranges
Table 131
I/O range, there may be separate behavior for reads and writes. The hub interface cycles that go to
target ranges that are marked as “Reserved” will not be decoded by the ICH5, and will be passed to
PCI. If a PCI master targets one of the fixed I/O target ranges, it will be positively decoded by the
ICH5 in Medium speed.
Refer to
marked “Reserved” are not decoded by the ICH5 (unless assigned to one of the variable ranges).
Table 205
Table 204
shows the Fixed I/O decode ranges from the processor perspective. Note that for each
for a complete list of all fixed I/O registers. Address ranges that are not listed or
for a complete list of all PCI Configuration Registers.
Register and Memory Mapping
269