FW82801EB Intel, FW82801EB Datasheet - Page 273

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

6.4
Intel
®
Table 133. Memory Decode Ranges from Processor Perspective (Sheet 1 of 2)
82801EB ICH5 / 82801ER ICH5R Datasheet
Memory Map
Table 133
Cycles that arrive from the hub interface that are not directed to any of the internal memory targets
that decode directly from hub interface will be driven out on PCI. The ICH5 may then claim the
cycle for it to be forwarded to LPC or claimed by the internal APIC. If subtractive decode is
enabled, the cycle can be forwarded to LPC.
PCI cycles generated by an external PCI master are positively decoded unless they falls in the
PCI-to-PCI bridge forwarding range (those addresses are reserved for PCI peer-to-peer traffic). If
the cycle is not in the I/O APIC or LPC ranges, it is forwarded up the hub interface to the host
controller. PCI masters can not access the memory ranges for functions that decode directly from
hub interface.
Memory Range
0000 0000h–000D FFFFh
0010 0000h–TOM
000E 0000h–000F FFFFh
FEC0 0000h–FEC0 0100h
FFC0 0000h–FFC7 FFFFh
FF80 0000h–FF87 FFFFh
FFC8 0000h–FFCF FFFFh
FF88 0000h–FF8F FFFFh
FFD0 0000h–FFD7 FFFFh
FF90 0000h–FF97 FFFFh
FFD8 0000h–FFDF FFFFh
FF98 0000h–FF9F FFFFh
FFE0 000h–FFE7 FFFFh
FFA0 0000h–FFA7 FFFFh
FFE8 0000h–FFEF FFFFh
FFA8 0000h–FFAF FFFFh
FFF0 0000h–FFF7 FFFFh
FFB0 0000h–FFB7 FFFFh
FFF8 0000h–FFFF FFFFh
FFB8 0000h–FFBF FFFFh
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
4 KB anywhere in 4 GB
range
1 KB anywhere in 4 GB
range
(Top of Memory)
shows (from the processor perspective) the memory ranges that the ICH5 decodes.
I/O APIC inside ICH5
IDE Expansion
Integrated LAN
Main Memory
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Flash BIOS
Controller
Target
2
Bit 7 in flash BIOS decode enable register is set
Always enabled.
The top two, 64-KB blocks of this range can be
swapped, as described in
Enable via BAR in Device 29:Function 0 (Integrated
LAN Controller)
Enable via standard PCI mechanism and bits in IDE
I/O Configuration Register (Device 31, Function 1)
TOM registers in host controller
Bit 0 in flash BIOS decode enable register
Bit 1 in flash BIOS decode enable register
Bit 2 in flash BIOS decode enable register is set
Bit 3 in flash BIOS decode enable register is set
Bit 4 in flash BIOS decode enable register is set
Bit 5 in flash BIOS decode enable register is set
Bit 6 in flash BIOS decode enable register is set.
Bit 3 in flash BIOS decode enable 2 register is set
Bit 2 in flash BIOS decode enable 2 register is set
Bit 1 in flash BIOS decode enable 2 register is set
Bit 0 in flash BIOS decode enable 2 register is set
Register and Memory Mapping
Dependency/Comments
Section
7.4.1.
273