FW82801EB Intel, FW82801EB Datasheet - Page 278

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.1.4
278
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS—PCI Status Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
effect.
10:9
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — R/WC.
0 = Parity error not detected.
1 = The Intel
Signaled System Error (SSE) — R/WC.
0 = Integrated LAN Controller has not asserted SERR#
1 = The ICH5’s integrated LAN controller has asserted SERR#. SERR# can be routed to cause
Master Abort Status ( RMA) — R/WC.
0 = this bit is cleared by writing a 1 to the bit location.
1 = The ICH5’s integrated LAN controller (as a PCI master) has generated a master abort.
Received Target Abort (RTA) — R/WC.
0 = Target abort not received.
1 = The ICH5’s integrated LAN controller (as a PCI master) has received a target abort.
Signaled Target Abort (STA) — RO. Hardwired to 0. The device will never signal Target Abort.
DEVSEL# Timing Status (DEV_STS) — RO.
01h = Medium timing.
Data Parity Error Detected (DPED) — R/WC.
0 = Parity error not detected (conditions below are not met).
1 = All of the following three conditions have been met:
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. The device can accept fast back-to-
back transactions.
User Definable Features (UDF) — RO. Hardwired to 0. Not implemented.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. The device does not support 66 MHz PCI.
Capabilities List (CAP_LIST) — RO.
0 = The EEPROM indicates that the integrated LAN controller does not support PCI Power
1 = The EEPROM indicates that the integrated LAN controller supports PCI Power Management.
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is independent from
the state of the Interrupt Enable bit in the command register.
Reserved
1.The LAN controller is acting as bus master
2.The LAN controller has asserted PERR# (for reads) or detected PERR# asserted (for writes)
3.The Parity Error Response bit in the LAN controller’s PCI Command Register is set.
set even if Parity Error Response is disabled in the PCI Command register).
NMI, SMI#, or interrupt.
Management.
06
0290h
®
–
07h
ICH5’s integrated LAN controller has detected a parity error on the PCI bus (will be
Description
Intel
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO, R/WC
16 bits