FW82801EB Intel, FW82801EB Datasheet - Page 280

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.1.8
7.1.9
7.1.10
280
CLS—Cache Line Size Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
PMLT—Primary Master Latency Timer Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
Bit
7:5
4:3
2:0
Bit
7:3
2:0
Bit
6:0
7
Reserved
Cache Line Size (CLS) — RW.
00 = Memory Write and Invalidate (MWI) command will not be used by the integrated LAN
01 = MWI command will be used with Cache Line Size set to 8 DWords (only set if a value of 08h is
10 = MWI command will be used with Cache Line Size set to 16 DWords (only set if a value of 10h
11 = Invalid. MWI command will not be used.
Reserved
Master Latency Timer Count (MLTC) — R/W. This field defines the number of PCI clock cycles
that the integrated LAN controller may own the bus while acting as bus master.
Reserved
Multi-Function Device (MFD) — RO. Hardwired to 0 to indicate a single function device.
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the configuration space
as an ethernet controller.
controller.
written to this register).
is written to this register).
0Ch
00h
0Dh
00h
0Eh
00h
Intel
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RW
8 bits
R/W
8 bits
RO
8 bits