FW82801EB Intel, FW82801EB Datasheet - Page 285

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

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7.1.23
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PMCSR — Power Management Control/Status Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
14:13
12:9
7:5
3:2
1:0
Bit
15
8
4
PME Status (PME_STAT) — R/WC.
0 = Software clears this bit by writing a 1 to it. This also deasserts the PME# signal and clears the
1 = Set upon occurrence of a wake-up event, independent of the state of the PME Enable bit.
Data Scale (DSCALE) — RO. This field indicates the data register scaling factor. It equals 10b for
registers 0 through eight and 00b for registers nine through fifteen, as selected by the “Data Select”
field.
Data Select (DSEL) — R/W. This field is used to select which data is reported through the Data
register and Data Scale field.
PME Enable (PME_EN) — R/W. This bit enables the Intel
assert PME#.
0 = The device will not assert PME#.
1 = Enable PME# assertion when PME Status is set.
Reserved
Dynamic Data (DYN_DAT) — RO. Hardwired to 0 to indicate that the device does not support the
ability to monitor the power consumption dynamically.
Reserved
Power State (PWR_ST) — R/W. This 2-bit field is used to determine the current power state of the
integrated LAN controller, and to put it into a new power state. The definition of the field values is as
follows:
00 = D0
01 = D1
10 = D2
11 = D3
PME status bit in the Power Management Driver Register. When the PME# signal is enabled,
the PME# signal reflects the state of the PME status bit.
E0
0000h
E1h
Description
Attribute:
Size:
LAN Controller Registers (B1:D8:F0)
®
ICH5’s integrated LAN controller to
RO, R/W, R/WC
16 bits
285

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