FW82801EB Intel, FW82801EB Datasheet - Page 288

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.2.1
288
SCB_STA—System Control Block Status Word Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
The ICH5’s integrated LAN controller places the status of its Command Unit (CU) and Receive
Unit (RC) and interrupt indications in this register for the processor to read.
Bit
7:6
15
14
13
12
11
10
9
8
Command Unit (CU) Executed (CX) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Interrupt signaled because the CU has completed executing a command with its interrupt bit
Frame Received (FR) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame.
CU Not Active (CNA) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = The Command Unit left the Active state or entered the Idle state. There are two, distinct states
Receive Not Ready (RNR) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Interrupt signaled because the Receive Unit left the Ready state. This may be caused by an RU
Management Data Interrupt (MDI) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Set when a Management Data Interface read or write cycle has completed. The management
Software Interrupt (SWI) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Set when software generates an interrupt.
Early Receive (ER) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Indicates the occurrence of an Early Receive interrupt.
Flow Control Pause (FCP) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Indicates Flow Control Pause interrupt.
Command Unit Status (CUS) — RO.
00 = Idle
01 = Suspended
10 = LPQ (Low Priority Queue) active
11 = HPQ (High Priority Queue) active
set.
of the CU. When configured to generate CNA interrupt, the interrupt will be activated when the
CU leaves the Active state and enters either the Idle or the Suspended state. When configured
to generate CI interrupt, an interrupt will be generated only when the CU enters the Idle state.
Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame
Descriptor.
data interrupt is enabled through the interrupt enable bit (bit 29 in the Management Data
Interface Control register in the CSR).
00
0000h
–
01h
Description
Intel
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC, RO
16 bits