FW82801EB Intel, FW82801EB Datasheet - Page 307

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

8.1.13
8.1.14
8.1.15
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
SMLT—Secondary Master Latency Timer Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
This Master Latency Timer (MLT) controls the amount of time that the ICH5 will continue to burst
data as a master on the PCI bus. When the ICH5 starts the cycle after being granted the bus, the
counter is loaded and starts counting down from the assertion of FRAME#. If the internal grant to
this device is removed, then the expiration of the MLT counter will result in the deassertion of
FRAME#. If the internal grant has not been removed, then the ICH5 can continue to own the bus.
IOBASE—I/O Base Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
IOLIM—I/O Limit Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
Bit
7:3
2:0
Bit
7:4
3:0
Bit
7:4
3:0
Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of PCI clocks, in
8-clock increments, that the Intel
Reserved
I/O Address Base Bits [15:12] — R/W. I/O This field provides base bits corresponding to address
lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Addressing Capability — RO. This field is hardwired to 0h indicating that the hub interface to PCI
bridge does not support 32-bit I/O addressing. This means that the I/O Base and Limit Upper
Address registers must be read only.
I/O Address Limit Bits [15:12] — R/W. I/O This field provides base bits corresponding to address
lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
I/O Addressing Capability — RO. This field is hardwired to 0h indicating that the hub interface-to-PCI
bridge does not support 32-bit I/O addressing. This means that the I/O Base and Limit Upper
Address registers must be read only.
1Bh
00h
1Ch
F0h
1Dh
00h
®
ICH5 remains as master of the bus.
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/W, RO
8 bits
R/W, RO
8 bits
307