FW82801EB Intel, FW82801EB Datasheet - Page 308

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.16
308
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
SECSTS—Secondary Status Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
effect.
10:9
Bit
4:0
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE) — R/WC.
0 = Parity error not detected.
1 = Intel
Received System Error (SSE) — R/WC.
0 = SERR# assertion not received
1 = SERR# assertion is received on PCI.
Received Master Abort (RMA) — R/WC.
0 = No master abort.
1 = Hub interface to PCI cycle is master-aborted on PCI.
Received Target Abort (RTA) — R/WC.
0 = No target abort.
1 = Hub interface to PCI cycle is target-aborted on PCI. For “completion required” cycles from the
Signaled Target Abort (STA) — RO. The ICH5 does not generate target aborts.
DEVSEL# Timing Status (DEV_STS) — RO.
01h = Medium timing.
Master Data Parity Error Detected (MDPD) — R/WC.
0 = Conditions described below not met.
1 = The ICH5 sets this bit when all of the following three conditions are met:
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1 to indicate that the PCI to hub interface
target logic is capable of receiving fast back-to-back cycles.
Reserved
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Reserved
- The Parity Error Response Enable bit in the Bridge Control Register (bit 0, offset 3Eh) is set.
- USB, AC ’97 or IDE is a Master.
- PERR# asserts during a write cycle OR a parity error is detected internally during a read cycle.
hub interface, this event should also set the Signaled Target Abort in the Primary Status
Register in this device, and the ICH5 must send the “target abort” status back to the hub
interface.
®
ICH5 detected a parity error on the PCI bus.
1E
0280h
–
1Fh
Description
Intel
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC, RO
16 bits