FW82801EB Intel, FW82801EB Datasheet - Page 314

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

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Hub Interface to PCI Bridge Registers (D30:F0)
8.1.27
314
CNF—Policy Configuration Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
31:24
23:20
17:16
15:14
12:10
Bit
7:3
19
18
13
9
8
2
1
0
Reserved
Async Reads — R/W.
ICH5 memory async read request. BIOS should set this value to 0111b.
BIOS should set this bit if the platform uses HI11.
BIOS should set this bit if the platform uses HI11.
PCI Prefetch — R/W.
PCI Prefetch request for PCI reads from main memory. BIOS should set this value to 11b.
Reserved
Prefetch Flush Enable — R/W.
0 = Prefetch Flush Disable
1 = Causes CPU to PCI logic to only deliver “Demand” data for a delayed transaction if a processor-
to-PCI write has occurred since the delayed transaction was initiated. (Default)
NOTE: This bit must be set by system BIOS.
Reserved
High Priority PCI Enable (HP_PCI_EN) — R/W.
0 = All PCI REQ#/GNT pairs have the same arbitration priority.
1 = Enables a mode where the REQ0#/GNT0# signal pair has a higher arbitration priority.
Hole Enable (15 MB – 16 MB) — R/W.
0 = Disable
1 = Enables the 15-MB to 16-MB hole in the DRAM.
Reserved
Delayed Transaction Discard Timer — R/W.
When set to 1 this bit shortens all delayed transaction discard timers from 32 µs to 4 µs.
NOTE: Setting this bit may improve system performance issues with certain non-optimally behaved
12-Clock Retry Enable — R/W. System BIOS must set this bit for PCI compliance.
0 = The Intel
1 = The ICH5 retries a PCI to memory cycle (reads or write) if the ICH5 is not able to complete the
Reserved
transfer in 12 PCI clocks.
PCI devices, but may violate the PCI-to-PCI Bridge Architecture Specification, Revision 1.1
(section 5.3.2)
50
00406402h
®
ICH5 inserts as many wait-states as needed to complete the PCI to memory cycle.
53h
Description
Intel
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
32 bits

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