FW82801EB Intel, FW82801EB Datasheet - Page 315

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

8.1.28
8.1.29
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: Programming the a value of 00h disables this function, which could cause starvation problems for
Note: Software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect.
MTT—Multi-Transaction Timer Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
MTT is an 8-bit register that controls the amount of time that the ICH5’s arbiter allows a PCI
initiator to perform multiple back-to-back transactions on the PCI bus. The ICH5’s MTT
mechanism is used to guarantee a fair share of the Primary PCI bandwidth to an initiator that
performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence
it can not use long burst transfers).
The number of clocks programmed in the MTT represents the guaranteed time slice (measured in
PCI clocks) allotted to the current agent, after which the arbiter will grant another agent that is
requesting the bus. The MTT value must be programmed with 8-clock granularity in the same
manner as MLT. For example, if the MTT is programmed to 18h, then the selected value
corresponds to the time period of 24 PCI clocks.The default value of MTT is 20h (32 PCI clocks).
some PCI master devices. Programming of the MTT to anything less than 16 clocks will not allow
the Grant-to-FRAME# latency to be 16 clocks. The MTT timer will timeout before the Grant-to-
FRAME# trigger causing a re-arbitration.
PCI_MAST_STS—PCI Master Status Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
Bit
7:3
2:0
Bit
5:0
7
6
Multi-Transaction Timer Count Value — R/W. This field specifies the amount of time that grant will
remain asserted to a master continuously asserting its request for multiple transfers. This field
specifies the count in an 8-clock (PCI clock) granularity.
Reserved
Internal PCI Master Request Status (INT_MREQ_STS) — R/WC.
0 = DMA controller or LPC has not requested use of the PCI bus.
1 = The Intel
Internal LAN Master Request Status (LAN_MREQ_STS) — R/WC.
0 = LAN controller has not requested use of the PCI bus.
1 = The ICH5’s internal LAN controller has requested use of the PCI bus.
PCI Master Request Status (PCI_MREQ_STS) — R/WC. Allows software to see if a particular bus
master has requested use of the PCI bus. For example, bit 0 will be set if the ICH5 has detected
REQ0# asserted and bit 5 will be set if ICH5 detected REQ5# asserted.
0 = Associated PCI master has not requested use of the PCI bus.
1 = The associated PCI master has requested use of the PCI bus.
70h
20h
82h
00h
®
ICH5’s internal DMA controller or LPC has requested use of the PCI bus.
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/WC
8 bits
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