FW82801EB Intel, FW82801EB Datasheet - Page 316

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.30
8.1.31
316
Note: Software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect.
ERR_CMD—Error Command Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
Lockable:
This register configures the ICH5’s Device 30 responses to various system errors. The actual
assertion of the internal SERR# (routed to cause NMI# or SMI#) is enabled via the PCI Command
register.
ERR_STS—Error Status Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
Lockable:
This register records the cause of system errors in Device 30. The actual assertion of SERR# is
enabled via the PCI Command register.
Bit
7:3
1:0
Bit
7:3
2
2
1
0
Reserved
SERR# Enable on Receiving Target Abort (SERR_RTA_EN) — R/W.
0 = Disable
1 = Enable. When SERR_EN is set, the Intel
Reserved
Reserved
SERR# Due to Received Target Abort (SERR_RTA) — R/WC.
0 = Target abort not received.
1 = Intel
Reserved
PCI Parity Inversion State (PAR_INV) — R/WC.
0 = No parity errors on PCI.
1 = Parity errors may have occurred on PCI. This bit can be checked as part of the NMI# service
SERR_RTA is set.
routine.
®
ICH5 received a target abort. If SERR_EN, the ICH5 will also generate an SERR# when
90h
00h
No
92h
00h
No
Description
Description
Intel
®
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
ICH5 will report SERR# when SERR_RTA is set.
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
8-bit
Core
R/WC
8-bit
Core