FW82801EB Intel, FW82801EB Datasheet - Page 319

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.1.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCICMD—PCI COMMAND Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W.
0 = Disable
1 = Enable. Allow SERR# to be generated.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — R/W.
0 = No action is taken when detecting a parity error.
1 = The Intel
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 1.
Bus Master Enable (BME) — RO. Hardwired to 1 to indicate that bus mastering cannot be disabled
for function 0 (DMA/ISA Master).
Memory Space Enable (MSE) — RO. Hardwired to 1 to indicate that memory space cannot be
disabled for Function 0 (LPC I/F).
I/O Space Enable (IOSE) — RO. Hardwired to 1 to indicate that the I/O space cannot be disabled for
function 0 (LPC I/F).
04
000Fh
No
®
–
05h
ICH5 will take normal action when a parity error is detected.
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
R/W, RO
16-bit
Core
319