FW82801EB Intel, FW82801EB Datasheet - Page 320

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.4
320
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS—PCI Status Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
effect.
10:9
Bit
4:0
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE) — R/WC.
0 = PERR# not active
1 = PERR# signal goes active. Set even if the PER bit is 0.
Signaled System Error (SSE) — R/WC.
0 = SERR# on function 0 not generated with SERR_EN set.
1 = Set by the Intel
Master Abort Status (RMA) — R/WC.
0 = Master abort on PCI not generated due to LPC I/F master or DMA cycle.
1 = ICH5 generated a master abort on PCI due to LPC I/F master or DMA cycles.
Received Target Abort (RTA) — R/WC.
0 = Target abort not received during LPC I/F master or DMA cycles to PCI.
1 = ICH5 received a target abort during LPC I/F master or DMA cycles to PCI.
Signaled Target Abort (STA) — R/WC.
0 = Target abort not generated on PCI cycles claimed by ICH5 for conditions listed below.
1 = ICH5 generated a target abort condition on PCI cycles claimed by the ICH5 for ICH5 internal
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Medium Timing.
Data Parity Error Detected (DPED) — R/WC.
0 = All conditions listed below not met.
1 = Set when all three of the following conditions are met:
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1 to indicate that the ICH5, as a target,
can accept fast back-to-back transactions.
User Definable Features (UDF). Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Reserved.
function 0. The ERR_STS register can be read to determine the cause of the SERR#. The
SERR# can be routed to cause SMI#, NMI, or interrupt.
registers or for going to LPC I/F.
- The ICH5 is the initiator of the cycle,
- The ICH5 asserted PERR# (for reads) or observed PERR# (for writes), and
- The PER bit is set.
06
0280h
No
–
07h
®
ICH5 if the SERR_EN bit is set and the ICH5 generates an SERR# on
Intel
Description
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO, R/WC
16-bit
Core