FW82801EB Intel, FW82801EB Datasheet - Page 327

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.1.17
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
SIRQ_CNTL—Serial IRQ Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
Bit
5:2
1:0
7
6
Serial IRQ Enable (SIRQEN) — R/W.
0 = The buffer is input only and internally SERIRQ will be a 1.
1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.
Serial IRQ Mode Select (SIRQMD) — R/W.
0 = The serial IRQ machine will be in quiet mode.
1 = The serial IRQ machine will be in continuous mode.
NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for at least one
Serial IRQ Frame Size (SIRQSZ) — R/W. Fixed field that indicates the size of the SERIRQ frame. In
the ICH5, this field needs to be programmed to 21 frames (0100). This is an offset from a base of 17
which is the smallest data frame size.
Start Frame Pulse Width (SFPW) — R/W. This is the number of PCI clocks that the SERIRQ pin will
be driven low by the serial IRQ machine to signal a start frame. In continuous mode, the ICH5 will
drive the start frame for the number of clocks specified. In quiet mode, the ICH5 will drive the start
frame for the number of clocks specified minus 1, as the first clock was driven by the peripheral.
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved
frame after coming out of reset before switching back to Quiet Mode. Failure to do so will
result in the Intel
64h
10h
No
®
ICH5 not recognizing SERIRQ interrupts.
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
R/W
8 bit
Core
327