FW82801EB Intel, FW82801EB Datasheet - Page 331

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
5:4
Bit
9
8
7
6
3
2
1
0
Top_Swap Lock-Down — R/WO. This bit can only be written from 0 to 1 once.
0 = A hardware reset is required to clear this bit.
1 = Prevents the top-swap bit from being changed.
APIC Enable (APIC_EN) — R/W.
0 = Disables internal I/O (x) APIC.
1 = Enables the internal I/O (x) APIC and its address decode.
The following behavioral rules apply for bits 8 and 7 in this register:
NOTE: There is no separate way to disable PCI Message Interrupts if the I/O (x) APIC is enabled.
System Bus Message Disable — R/W.
0 = Has no effect. (Default)
1 = Disables the ICH5 IOAPIC controller from generating anymore system bus interrupt
NOTE: It is possible for the ICH5 to deliver up to 1 system bus interrupt message from the time
Alternate Access Mode Enable (ALTACC_EN) — R/W.
0 = Disable (default). ALT access mode allows reads to otherwise unreadable registers and writes
1 = Enable
Reserved
Reserved— RO.
DMA Collection Buffer Enable (DCB_EN) — R/W.
0 = DCB disabled.
1 = Enables DMA Collection Buffer (DCB) for LPC I/F and PC/PCI DMA.
Delayed Transaction Enable (DTE) — R/W.
0 = Disable
1 = Enable. ICH5 enables delayed transactions for internal register, flash BIOS and LPC I/F
Positive Decode Enable (POS_DEC_EN) — R/W.
0 = Disable. The ICH5 performs subtractive decode on the PCI bus and forwards the cycles to
1 = Enables ICH5 to only perform positive decode on the PCI bus.
• Rule 1: If bit 8 is 0, then the ICH5 will not decode any of the registers associated with the I/O
• Rule 2: If bit 8 is 1 and bit 7 is 0, then the ICH5 will decode the memory space associated with
• Rule 3: If bit 8 is 1 and bit 7 is 1, then the ICH5 will decode the memory space associated with
APIC or I/O (x) APIC. The state of bit 7 is “Don’t Care” in this case.
the I/O APIC, but not the extra registers associated I/O (x) APIC.
both the I/O APIC and the I/O (x) APIC. This also enables PCI masters to write directly to the
register to cause interrupts (PCI Message Interrupt).
messages.
otherwise unwritable registers.
accesses.
LPC I/F if not to an internal register or other known target on LPC I/F. Accesses to internal
registers and to known LPC I/F devices are still positively decoded.
This is not considered necessary.
this configuration bit is set to 1.
Description
LPC Interface Bridge Registers (D31:F0)
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