FW82801EB Intel, FW82801EB Datasheet - Page 34

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Contents
34
50 Interrupt Message Data Format................................................................................................ 134
51 Stop Frame Explanation ........................................................................................................... 136
52 Data Frame Format .................................................................................................................. 137
53 Configuration Bits Reset by RTCRST# Assertion .................................................................... 140
54 INIT# Going Active ................................................................................................................... 142
55 NMI Sources ............................................................................................................................. 143
56 DP Signal Differences .............................................................................................................. 143
57 Frequency Strap Behavior Based on Exit State ....................................................................... 144
58 Frequency Strap Bit Mapping ................................................................................................... 145
59 General Power States for Systems Using Intel
60 State Transition Rules for Intel
61 System Power Plane ................................................................................................................ 148
62 Causes of SMI# and SCI .......................................................................................................... 149
63 Sleep Types.............................................................................................................................. 152
64 Causes of Wake Events ........................................................................................................... 153
65 GPI Wake Events ..................................................................................................................... 153
66 Transitions Due to Power Failure ............................................................................................. 154
67 Transitions Due to Power Button .............................................................................................. 156
68 Transitions Due to RI# Signal ................................................................................................... 157
69 Write Only Registers with Read Paths in ALT Access Mode ................................................... 159
70 PIC Reserved Bits Return Values ............................................................................................ 161
71 Register Write Accesses in ALT Access Mode ........................................................................ 161
72 Intel
73 Heartbeat Message Data.......................................................................................................... 169
74 GPIO Implementation ............................................................................................................... 170
75 IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select).................................. 175
76
77 Interrupt/Active Bit Interaction Definition .................................................................................. 180
78 UltraATA/33 Control Signal Redefinitions................................................................................. 181
79 SATA MSI vs. PCI IRQ Actions ................................................................................................ 188
80 Legacy Routing......................................................................................................................... 189
81 Frame List Pointer Bit Description ............................................................................................ 192
82 TD Link Pointer ......................................................................................................................... 193
83 TD Control and Status .............................................................................................................. 194
84 TD Token.................................................................................................................................. 196
85 TD Buffer Pointer ...................................................................................................................... 196
86 Queue Head Block ................................................................................................................... 197
87 Queue Head Link Pointer ......................................................................................................... 197
88 Queue Element Link Pointer..................................................................................................... 197
89 Command Register, Status Register and TD Status Bit Interaction ......................................... 200
90 Queue Advance Criteria ........................................................................................................... 202
91 USB Schedule List Traversal Decision Table ........................................................................... 203
92 PID Format ............................................................................................................................... 205
93 PID Types ................................................................................................................................. 205
94 Address Field............................................................................................................................ 206
95 Endpoint Field........................................................................................................................... 206
96 Token Format ........................................................................................................................... 207
97 SOF Packet .............................................................................................................................. 207
98 Data Packet Format.................................................................................................................. 208
99 Bits Maintained in Low Power States ....................................................................................... 212
IDE Transaction Timings (PCI Clocks) .................................................................................... 176
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ICH5 Clock Inputs........................................................................................................... 163
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ICH5 ...................................................................................... 147
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ICH5 ............................................................. 146
Intel
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82801EB ICH5 / 82801ER ICH5R Datasheet