FW82801EB Intel, FW82801EB Datasheet - Page 345

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.2.1
Intel
®
Table 142. DMA Registers (Sheet 2 of 2)
82801EB ICH5 / 82801ER ICH5R Datasheet
DMABASE_CA—DMA Base and Current Address Registers
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
15:0
Bit
Port
DCh
CEh
DAh
DEh
D0h
D4h
D6h
D8h
Base and Current Address — R/W. This register determines the address for the transfers to be
performed. The address specified points to two separate registers. On writes, the value is stored in
the Base Address register and copied to the Current Address register. On reads, the value is
returned from the Current Address register.
The address increments/decrements in the Current Address register after each transfer, depending
on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register will
be reloaded from the Base Address register after a terminal count is generated.
For transfers to/from a 16-bit slave (channel’s 5-7), the address is shifted left one bit location. Bit 15
will be shifted into Bit 16.
The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop.
Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the
low byte is accessed first
Alias
DBh
DDh
CFh
D1h
D5h
D7h
D9h
DFh
Ch. #0 = 00h; Ch. #1 = 02h
Ch. #2 = 04h; Ch. #3 = 06h
Ch. #5 = C4h Ch. #6 = C8h
Ch. #7 = CCh;
Undef
No
Channel 7 DMA Base & Current Count
Channel 4–7 DMA Command
Channel 4–7 DMA Status
Channel 4–7 DMA Write Single Mask
Channel 4–7 DMA Channel Mode
Channel 4–7 DMA Clear Byte Pointer
Channel 4–7 DMA Master Clear
Channel 4–7 DMA Clear Mask
Channel 4–7 DMA Write All Mask
Register Name
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
R/W
16 bit (per channel),
but accessed in two 8-bit
quantities
Core
000001XXb
000000XXb
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Default
0Fh
Type
R/W
R/W
WO
WO
WO
WO
WO
WO
RO
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