FW82801EB Intel, FW82801EB Datasheet - Page 347

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.2.4
9.2.5
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
DMACMD—DMA Command Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
DMASTA—DMA Status Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bit
7:5
1:0
Bit
7:4
3:0
4
3
2
Reserved. Must be 0.
DMA Group Arbitration Priority — WO. Each channel group is individually assigned either fixed or
rotating arbitration priority. At part reset, each group is initialized in fixed priority.
0 = Fixed priority to the channel group
1 = Rotating priority to the group.
Reserved. Must be 0
DMA Channel Group Enable — WO. Both channel groups are enabled following part reset.
0 = Enable the DMA channel group.
1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is cascaded
Reserved. Must be 0.
Channel Request Status — RO. When a valid DMA request is pending for a channel, the
corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the
corresponding bit is set to 0. The source of the DREQ may be hardware or a software request. Note
that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the
request status for channels 0 through 3.
4 = Channel 0
5 = Channel 1 (5)
6 = Channel 2 (6)
7 = Channel 3 (7)
Channel Terminal Count Status — RO. When a channel reaches terminal count (TC), its status bit
is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for
cascade, so the TC bit response for channel 4 is irrelevant:
0 = Channel 0
1 = Channel 1 (5)
2 = Channel 2 (6)
3 = Channel 3 (7)
through channel 4.
Ch. #0
Ch. #4
Undefined
No
Ch. #0
Ch. #4
Undefined
No
–
–
–
–
3 = 08h;
7 = D0h
3 = 08h;
7 = D0h
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
WO
8-bit
Core
RO
8-bit
Core
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