FW82801EB Intel, FW82801EB Datasheet - Page 35

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Contents
100 USB Legacy Keyboard State Transitions .................................................................................214
101 UHCI vs. EHCI..........................................................................................................................215
102 Debug Port Behavior ................................................................................................................227
103 Quick Protocol ..........................................................................................................................232
104 Send / Receive Byte Protocol without PEC ..............................................................................232
105 Send/Receive Byte Protocol with PEC .....................................................................................233
106 Write Byte/Word Protocol without PEC.....................................................................................233
107 Write Byte/Word Protocol with PEC..........................................................................................234
108 Read Byte/Word Protocol without PEC ....................................................................................235
109 Read Byte/Word Protocol with PEC .........................................................................................235
110 Process Call Protocol without PEC...........................................................................................236
111 Process Call Protocol with PEC................................................................................................237
112 Block Read/Write Protocol without PEC ...................................................................................238
113 Block Read/Write Protocol with PEC ........................................................................................239
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114 I
C Block Read .........................................................................................................................240
115 Block Write–Block Read Process Call Protocol with/without PEC............................................241
116 Enable for SMBALERT# ...........................................................................................................244
117 Enables for SMBus Slave Write and SMBus Host Events........................................................244
118 Enables for the Host Notify Command .....................................................................................244
119 Slave Write Cycle Format .........................................................................................................246
120 Slave Write Registers ...............................................................................................................246
121 Command Types ......................................................................................................................247
122 Read Cycle Format...................................................................................................................248
123 Data Values for Slave Read Registers .....................................................................................249
124 Host Notify Format....................................................................................................................250
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125 Features Supported by Intel
ICH5 ..........................................................................................251
126 AC ’97 Signals ..........................................................................................................................254
127 Input Slot 1 Bit Definitions.........................................................................................................260
128 Output Tag Slot 0......................................................................................................................262
129 AC-link State during PCIRST#..................................................................................................264
130 PCI Devices and Functions ......................................................................................................268
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131 Fixed I/O Ranges Decoded by Intel
ICH5 ..............................................................................270
132 Variable I/O Decode Ranges ....................................................................................................272
133 Memory Decode Ranges from Processor Perspective.............................................................273
134 LAN Controller PCI Register Address Map (LAN Controller—B1:D8:F0).................................275
135 Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM................................282
136 Data Register Structure ............................................................................................................286
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137 Intel
ICH5 Integrated LAN Controller CSR Space Register Address Map .............................287
138 Self-Test Results Format ..........................................................................................................292
139 Statistical Counters...................................................................................................................299
140 Hub Interface PCI Register Address Map (HUB-PCI—D30:F0) ...............................................301
141 LPC Interface PCI Register Address Map (LPC I/F—D31:F0) .................................................317
142 DMA Registers..........................................................................................................................344
143 PIC Registers (LPC I/F—D31:F0).............................................................................................355
144 APIC Direct Registers (LPC I/F—D31:F0)................................................................................363
145 APIC Indirect Registers (LPC I/F—D31:F0) .............................................................................363
146 RTC I/O Registers (LPC I/F—D31:F0) .....................................................................................369
147 RTC (Standard) RAM Bank (LPC I/F—D31:F0) .......................................................................369
148 Processor Interface PCI Register Address Map (LPC I/F—D31:F0) ........................................373
149 Power Management PCI Register Address Map (PM—D31:F0)..............................................376
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Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
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