FW82801EB Intel, FW82801EB Datasheet - Page 358

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.4.5
9.4.6
358
ICW3—Slave Controller Initialization Command Word 3
Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
ICW4—Initialization Command Word 4 Register
(LPC I/F—D31:F0)
Offset Address:
Bit
7:3
2:0
Bit
7:5
4
3
2
1
0
0 = These bits must be programmed to 0.
Slave Identification Code — WO. These bits are compared against the slave identification code
broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the
trailing edge of the second internal INTA# pulse. These bits must be programmed to 02h to match
the code broadcast by the master controller. When 02h is broadcast by the master controller during
the INTA# sequence, the slave controller assumes responsibility for broadcasting the interrupt
vector.
0 = These bits must be programmed to 0.
Special Fully Nested Mode (SFNM) — WO.
0 = Should normally be disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed.
Buffered Mode (BUF) — WO.
0 = Must be programmed to 0 for the Intel
Master/Slave in Buffered Mode — WO. Not used.
0 = Should always be programmed to 0.
Automatic End of Interrupt (AEOI) — WO.
0 = This bit should normally be programmed to 0. This is the normal end of interrupt.
1 = Automatic End of Interrupt (AEOI) mode is programmed.
Microprocessor Mode — WO.
1 = Must be programmed to 1 to indicate that the controller is operating in an Intel
Architecture-based system.
A1h
All bits undefined
Master Controller
Slave Controller
–
–
0A1h
021h
®
Intel
Description
Description
ICH5. This is non-buffered mode.
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
WO
8 bits
WO
8 bits