FW82801EB Intel, FW82801EB Datasheet - Page 369

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.6
9.6.1
Intel
®
Table 146. RTC I/O Registers (LPC I/F—D31:F0)
Table 147. RTC (Standard) RAM Bank (LPC I/F—D31:F0)
82801EB ICH5 / 82801ER ICH5R Datasheet
Real Time Clock Registers (LPC I/F—D31:F0)
I/O Register Address Map (LPC I/F—D31:F0)
The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the
standard and extended banks. The first 14 bytes of the standard bank contain the RTC time and date
information along with four registers, A
extended bank contains a full 128 bytes of battery backed SRAM, and will be accessible even when
the RTC module is disabled (via the RTC configuration register). Registers A
exist in the RAM.
All data movement between the host processor and the real-time clock is done through registers
mapped to the standard I/O space. The register map appears in
NOTES:
The RTC contains two sets of indexed registers that are accessed using the two separate Index and
Target registers (70/71h or 72/73h), as shown in
1. I/O locations 70h and 71h are the standard ISA location for the real-time clock. The map for this bank is
2. Software must preserve the value of bit 7 at I/O addresses 70h. When writing to this address, software must
I/O Locations
70h and 74h
71h and 75h
72h and 76h
73h and 77h
shown in
also accessed using an indexed scheme. I/O address 72h is used as the address pointer and I/O address
73h is used as the data register. Index addresses above 127h are not valid. If the extended RAM is not
needed, it may be disabled.
first read the value, and then write the same value for bit 7 during the sequential address write. Note that port
70h is not directly readable. The only way to read this register is through Alt Access mode. If the NMI# enable
is not changed during normal operation, software can alternatively read this bit once and then retain the value
for all subsequent writes to port 70h.
0Eh–7Fh
Index
0Ah
0Bh
0Ch
0Dh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
Table
147. Locations 72h and 73h are for accessing the extended RAM. The extended RAM bank is
Also alias to 72h and 76h
Also alias to 73h and 77h
Seconds
Seconds Alarm
Minutes
Minutes Alarm
Hours
Hours Alarm
Day of Week
Day of Month
Month
Year
Register A
Register B
Register C
Register D
114 Bytes of User RAM
If U128E bit = 0
Name
–
D, that are used for configuration of the RTC. The
Real-Time Clock (Standard RAM) Index Register
Real-Time Clock (Standard RAM) Target Register
Extended RAM Index Register (if enabled)
Extended RAM Target Register (if enabled)
Table
LPC Interface Bridge Registers (D31:F0)
147.
Table
Function
146.
–
D do not physically
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