FW82801EB Intel, FW82801EB Datasheet - Page 373

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.7
9.7.1
Intel
®
Table 148. Processor Interface PCI Register Address Map (LPC I/F—D31:F0)
82801EB ICH5 / 82801ER ICH5R Datasheet
NMI_SC—NMI Status and Control Register
Processor Interface Registers (LPC I/F—D31:F0)
Table 148
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Offset
Bit
CF9h
F0h
7
6
5
4
3
2
1
0
61h
70h
92h
SERR# NMI Source Status (SERR#_NMI_STS) — RO.
1 = PCI agent detected a system error and pulses the PCI SERR# line. This interrupt source is
IOCHK# NMI Source Status (IOCHK_NMI_STS) — RO.
1 = An ISA agent (via SERIRQ) asserted IOCHK# on the ISA bus. This interrupt source is enabled
Timer Counter 2 OUT Status (TMR2_OUT_STS) — RO. This bit reflects the current state of the
8254 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a
determinate value. When writing to port 61h, this bit must be a 0.
Refresh Cycle Toggle (REF_TOGGLE) — RO. This signal toggles from either 0 to 1 or 1 to 0 at a
rate that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be
a 0.
IOCHK# NMI Enable (IOCHK_NMI_EN) — R/W.
0 = Enabled.
1 = Disabled and cleared.
PCI SERR# Enable (PCI_SERR_EN) — R/W.
0 = SERR# NMIs are enabled.
1 = SERR# NMIs are disabled and cleared.
Speaker Data Enable ( SPKR_DAT_EN) — R/W.
0 = SPKR output is a 0.
1 = SPKR output is equivalent to the Counter 2 OUT signal value.
Timer Counter 2 Enable (TIM_CNT2_EN) — R/W.
0 = Disable
1 = Enable
is the register address map for the processor interface registers.
COPROC_ERR
enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When
writing to port 61h, this bit must be 0.
by setting bit 3 to 0. To reset the interrupt, set bit 3 to 0 and then set it to 1. When writing to port
61h, this bit must be a 0.
Mnemonic
RST_CNT
PORT92
NMI_SC
NMI_EN
61h
00h
No
NMI Status and Control
NMI Enable
Fast A20 and Init
Coprocessor Error
Reset Control
Register Name
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
R/W, RO
8-bit
Core
Default
00h
80h
00h
00h
00h
R/W (special)
R/W, RO
Type
R/W
R/W
WO
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