FW82801EB Intel, FW82801EB Datasheet - Page 378

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.2
378
GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)
Offset Address:
Default Value:
Lockable:
NOTE: VRMPWROK is sampled using the RTC clock. Therefore, low times that are less than one RTC clock
Bit
6:5
7
4
3
2
1
0
period may not be detected by the ICH5.
DRAM Initialization Bit — R/W. This bit does not effect hardware functionality in any way. BIOS is
expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after
completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence
was interrupted by a reset by reading this bit during the boot sequence.
Reserved
System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.
0 = SYS_RESET# button not pressed.
1 = Intel
NOTE: This bit is also reset by RSMRST# and CF9h resets.
CPU Thermal Trip Status (CTS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PCIRST# is inactive and CPUTHRMTRIP# goes active while the system is
NOTE: This bit is also reset by RSMRST# and CF9h resets. It is not reset by the shutdown and
Minimum SLP_S4# Assertion Width Violation Status — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time programmed in
NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some cases before
CPU Power Failure (CPUPWR_FLR) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low.
PWROK Failure (PWROK_FLR) — R/WC.
0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3 state.
1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1 state. The bit
NOTE: See
NOTE: In the case of true PWROK failure, PWROK will go low first before VRMPWRGD.
• If the bit is 1, then the DRAM initialization was interrupted.
• This bit is reset by the assertion of the RSMRST# pin.
this bit and clear it, if it is set.
in an S0 or S1 state.
the SLP_S4# Minimum Assertion Width field. When exiting G3, the ICH5 begins the timer when
the RSMRST# input deasserts. Note that this bit is functional regardless of the value in the
SLP_S4# Assertion Stretch Enable.
will be cleared only by software by writing a 1 to this bit or when the system goes to a G3 state.
reboot associated with the CPUTHRMTRIP# event.
the default value is readable.
®
ICH5 sets this bit when the SYS_RESET# button is pressed. BIOS is expected to read
A2h
00h
No
Section 5.13.11.3
for more details about the PWROK pin functionality.
Intel
Description
Attribute:
Size:
Usage:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W, R/WC
8-bit
ACPI, Legacy
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