FW82801EB Intel, FW82801EB Datasheet - Page 393

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Bit
8
7
6
5
4
3
RI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes active.
SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can independently
cause an SMI# or SCI, so this bit does not need to do so (unlike the other bits in this register).
Software clears this bit by writing a 1 to it.
0 = Wake event not caused by the ICH5’s SMBus logic.
1 = Set by hardware to indicate that the wake event was caused by the ICH5’s SMBus logic.This
NOTES:
TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = TOC logic did not cause SCI.
1 = Set by hardware when the TCO logic causes an SCI.
AC97_STS — R/WC. This bit will be set to 1 when the codecs are attempting to wake the system
and the PME events for the codecs are armed for wakeup. A PME is armed by programming the
appropriate PMEE bit in the Power Management Control and Status register at bit 8 of offset 54h
in each AC’97 function.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the codecs are attempting to wake the system. The AC97_STS bit
NOTE: This bit is not affected by a hard reset caused by a CF9h write.
USB2_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = USB UHCI controller 2 does not need to cause a wake.
1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake event will be
USB1_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = USB UHCI controller 1 does not need to cause a wake.
1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event will be
1. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the
2. If SMB_WAK_STS is set due to SMBus slave receiving a message, it will be cleared by
3. The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by software before
S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states,
software must clear this bit after each reception of the Wake/SMI# command or just prior to
entering the sleep state.
internal logic when a THRMTRIP# event happens or a Power Button Override event.
However, THRMTRIP# or Power Button Override event will not clear SMB_WAK_STS if it is
set due to SMBALERT# signal going active.
the SMB_WAK_STS bit is cleared.
bit will be set by the WAKE/SMI# command type, even if the system is already awake. The
SMI handler should then clear this bit.
gets set only from the following two cases:
generated if the corresponding USB2_EN bit is set.
generated if the corresponding USB1_EN bit is set.
1.The PMEE bit for the function is set, and o The AC-link bit clock has been shut and the
2.For modem, if audio routing is disabled, then the wake event is an OR of all AC_SDIN
routed AC_SDIN line is high (for audio, if routing is disabled, no wake events are allowed.
lines. If routing is enabled, then the wake event for modem is the remaining non-routed
AC_SDIN line), or o GPI Status Change Interrupt bit (NABMBAR + 30h, bit 0) is 1.
Description
LPC Interface Bridge Registers (D31:F0)
393