FW82801EB Intel, FW82801EB Datasheet - Page 395

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Bit
11
10
9
8
7
6
5
4
3
2
1
0
PME_EN — R/W.
0 = Disable
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be
Reserved
Reserved
RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not affected by a
hard reset caused by a CF9h write.
0 = Disable
1 = Enables the setting of the RI_STS to generate a wake event.
Reserved
TCOSCI_EN — R/W.
0 = Disable
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
AC97_EN — R/W.
0 = Disable
1 = Enables the setting of the AC97_STS to generate a wake event.
USB2_EN — R/W.
0 = Disable
1 = Enables the setting of the USB2_STS to generate a wake event.
USB1_EN — R/W.
0 = Disable
1 = Enables the setting of the USB1_STS to generate a wake event.
THRM#_POL — R/W. This bit controls the polarity of the THRM# pin needed to set the
THRM_STS bit.
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
Reserved
THRM_EN — R/W.
0 = Disable
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the
a wake event from the S1 – S4 state or from S5 (if entered via SLP_EN, but not power button
override).
THRM_STS bit and generate a power management event (SCI or SMI).
Description
LPC Interface Bridge Registers (D31:F0)
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