FW82801EB Intel, FW82801EB Datasheet - Page 405

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.11.5
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
TCO1_STS—TCO1 Status Register
I/O Address:
Default Value:
Lockable:
15:13
Bit
6:4
12
11
10
9
8
7
3
Reserved
HUBSERR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Intel
NOTE: If this bit is set AND the SERR_EN bit in CMD register (D30:F0, Offset 04h, bit 8) is also set,
HUBNMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH5 received an NMI message via the hub interface. The software must read the memory
HUBSMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH5 received an SMI message via the hub interface. The software must read the memory
HUBSCI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH5 received an SCI message via the hub interface. The software must read the memory
BIOSWR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH5 sets this bit and generates and SMI# to indicate an illegal attempt to write to the BIOS.
NOTE: On write cycles attempted to the 4-MB lower alias to the BIOS space, the BIOSWR_STS
NEWCENTURY_STS — R/WC. This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.
1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00.
Note that the NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when
RTC power has not been maintained). Software can determine if RTC power has not been
maintained by checking the RTC_PWR_STS bit, or by other means (such as a checksum on RTC
RAM). If RTC power is determined to have not been maintained, BIOS should set the time to a legal
value and then clear the NEWCENTURY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a 1 is
written to the bit to clear it. After writing a 1 to this bit, software should not exit the SMI handler until
verifying that the bit has actually been cleared. This will ensure that the SMI is not re-entered.
Reserved
TIMEOUT — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by ICH5 to indicate that the SMI was caused by the TCO timer reaching 0.
memory controller hub (or its equivalent) to determine the reason for the SERR#.
controller hub (or its equivalent) to determine the reason for the NMI.
controller hub (or its equivalent) to determine the reason for the SMI#.
controller hub (or its equivalent) to determine the reason for the SCI.
This occurs when either:
a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
b) any write is attempted to the BIOS and the BIOSWP bit is also set.
Setting this bit will cause an SMI# (but not a wake event).
the ICH5 will set the SSE bit in SECSTS register (D30:F0, offset 1Eh, bit 14) AND will also
generate a NMI (or SMI# if NMI routed to SMI#).
will not be set.
®
ICH5 received an SERR# message via the hub interface. The software must read the
TCOBASE +04h
0000h
No
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
R/WC, RO
16-bit
Core
(Except bit 7, in RTC)
405