FW82801EB Intel, FW82801EB Datasheet - Page 407

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.11.7
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
TCO1_CNT—TCO1 Control Register
I/O Address:
Default Value:
Lockable:
15:13
Bit
7:0
12
11
10
9
8
Reserved
TCO_LOCK — R/W (special). When set to 1, this bit prevents writes from changing the TCO_EN bit
(in offset 30h of Power Management I/O space). Once this bit is set to 1, it can not be cleared by
software writing a 0 to this bit location. A core-well reset is required to change this bit from 1 to 0.
This bit defaults to 0.
TCO Timer Halt (TCO_TMR_HLT) — R/W.
0 = The TCO Timer is enabled to count.
1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will cause an SMI#
SEND_NOW — R/W (special).
0 = The Intel
1 = Writing a 1 to this bit will cause the ICH5 to send an Alert On LAN Event message over the
Setting the SEND_NOW bit causes the ICH5 integrated LAN controller to reset, which can have
unpredictable side-effects. Unless software protects against these side effects, software should not
attempt to set this bit.
NMI2SMI_EN — R/W.
0 = Normal NMI functionality.
1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent upon the
NMI_EN
NMI_NOW — R/WC.
0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear this bit. Another
1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an entry to
Reserved
0
0
1
1
or set the SECOND_TO_STS bit. When set, this bit will prevent rebooting and prevent Alert On
LAN event messages from being transmitted on the SMLINK (but not Alert On LAN* heartbeat
messages).
not set this bit to 1 again until the ICH5 has set it back to 0.
SMLINK interface, with the Software Event bit set.
settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table:
NMI will not be generated until the bit is cleared.
the NMI handler.
TCOBASE +08h
0000h
No
GBL_SMI_EN
®
ICH5 will clear this bit when it has completed sending the message. Software must
0
1
0
1
Description
No SMI# at all because GBL_SMI_EN = 0
SMI# will be caused due to NMI events
No SMI# at all because GBL_SMI_EN = 0
No SMI# due to NMI because NMI_EN = 1
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
R/W, R/W (special), R/WC
16-bit
Core
407