FW82801EB Intel, FW82801EB Datasheet - Page 409

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.11.11
9.12
Intel
®
Table 153. Registers to Control GPIO Address Map
82801EB ICH5 / 82801ER ICH5R Datasheet
SW_IRQ_GEN—Software IRQ Generation Register
Offset Address:
Default Value:
Power Well:
General Purpose I/O Registers (D31:F0)
The control for the general purpose I/O signals is handled through a separate 64-byte I/O space.
The base offset for this space is selected by the GPIO_BAR register.
0C–0Fh
1C–1Fh
2C–2Fh
08–0Bh
18–1Bh
20–2Bh
38–3Bh
00–03h
04–07h
10–13h
14–17h
30–33h
34–37h
Offset
Bit
7:2
1
0
Reserved
IRQ12_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ12 signal as received by
the Intel
IRQ12 assertions from a SERIRQ device.
IRQ1_CAUSE — R/W. The state of this bit is logically ANDed with the IRQ1 signal as received by
the ICH5’s SERIRQ logic. This bit must be a 1 (default) if the ICH5 is expected to receive IRQ1
assertions from a SERIRQ device.
GPIO_USE_SEL2 GPIO Use Select 2
GPIO_USE_SEL
GP_IO_SEL2
GPO_BLINK
GP_IO_SEL
Mnemonic
GPO_TTL
GP_LVL2
GPI_INV
GP_LVL
®
ICH5’s SERIRQ logic. This bit must be a 1 (default) if the ICH5 is expected to receive
—
—
—
TCOBASE + 10h
11h
Core
GPIO Use Select
GPIO Input/Output Select
Reserved
GPIO Level for Input or Output
Reserved
Output Control Registers
GPIO TTL Select
GPIO Blink Enable
Reserved
Reserved
GPIO Signal Invert
GPIO Input/Output Select 2
GPIO Level for Input or Output 2
Input Control Registers
General Registers
Register Name
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
R/W
8 bits
0000 FFFFh
1F1F 0000h
1A003180h
06630000h
00000000h
00000000h
00000007h
00000300h
00030207h
Default
00h
—
—
—
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
—
—
—
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