FW82801EB Intel, FW82801EB Datasheet - Page 411

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.12.3
9.12.4
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
GP_LVL—GPIO Level for Input or Output Register
GPO_BLINK—GPO Blink Enable Register
Offset Address:
Default Value:
Lockable:
Offset Address:
Default Value:
Lockable:
NOTE: GPIO18 will blink by default immediately after reset. This signal could be connected to an LED to
31:29, 26
24:20, 17:0
31:29, 26,
28:27, 25
28:27,
25:24
23:16
15:0
19:18
Bit
Bit
indicate a failed boot (by programming BIOS to clear GP_BLINK18 after successful POST).
Reserved
GP_LVL[n] — R/W. If GPIOn is programmed to be an output (via the corresponding bit in the
GP_IO_SEL register) then the bit can be updated by software to drive a high or low value on the
output pin. If GPIOn is programmed as an input, then software can read the bit to determine the
level on the corresponding input pin. These bits correspond to GPIO that are in the Resume well,
and will be reset to their default values by RSMRST# and also by a write to the CF9h register.
0 = Low
1 = High
GP_LVL[n] — R/W. These bits can be updated by software to drive a high or low value on the
output pin. These bits correspond to GPIO that are in the core well, and will be reset to their
default values by PCIRST#.
0 = Low
1 = High
Reserved. For GPI[13:11] and [8:0], the active status of a GPI is read from the corresponding bit in
GPE0_STS register.
Reserved
GP_BLINK[n] — R/W. The setting of these bits will have no effect if the corresponding GPIO is
programmed as an input. These bits correspond to GPIO that are in the Resume well, and will
be reset to their default values by RSMRST# or by a write to the CF9h register.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate
GP_BLINK[n] — R/W. The setting of these bits will have no effect if the corresponding GPIO is
programmed as an input. These bits correspond to GPIO that are in the Core well, and will be
reset to their default values by PCIRST#.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will blink at a rate
of approximately once per second. The high and low times have approximately 0.5
seconds each. The GP_LVL bit is not altered when this bit is set.
of approximately once per second. The high and low times are approximately 0.5 seconds
each. The GP_LVL bit is not altered when this bit is set.
GPIOBASE +0Ch
1B3F 0000h
No
GPIOBASE +18h
0004 0000h
No
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
32-bit
See bit descriptions
R/W
32-bit
See bit description
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