FW82801EB Intel, FW82801EB Datasheet - Page 43

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Introduction
The following sub-sections provide an overview of the ICH5 capabilities.
Hub Architecture
The chipset’s hub interface architecture ensures that the I/O subsystem; both PCI and the integrated
I/O features (SATA, IDE, AC ‘97, USB, etc.), receive the bandwidth necessary for peak
performance.
PCI Interface
The ICH5 PCI interface provides a 33 MHz, Revision 2.3 compliant implementation. All PCI
signals are 5-V tolerant, except PME#. The ICH5 integrates a PCI arbiter that supports up to six
external PCI bus masters in addition to the internal ICH5 requests.
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks
and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports
PIO IDE transfers up to 16 Mbytes/sec and Ultra ATA transfers up 100 Mbytes/sec. It does not
consume any ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal
transfers.
The ICH5’s IDE system contains two independent IDE signal channels. They can be electrically
isolated independently. They can be configured to the standard primary and secondary channels
(four devices). There are integrated series resistors on the data and control lines (see
Section 5.16
for details).
SATA Controller
The SATA controller supports two SATA devices providing an interface for SATA hard disks and
ATAPI devices. The SATA interface supports PIO IDE transfers up to 16 Mb/s and Serial ATA
transfers up to 1.5 Gb/s (150 MB/s).
The ICH5’s SATA system contains two independent SATA signal ports. They can be electrically
isolated independently. Each SATA device can have independent timings. They can be configured
to the standard primary and secondary channels.
Low Pin Count (LPC) Interface
The ICH5 implements an LPC Interface as described in the Low Pin Count Interface Specification,
Revision 1.1. The Low Pin Count (LPC) Bridge function of the ICH5 resides in PCI
Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other
functional units including DMA, interrupt controllers, timers, power management, system
management, GPIO, and RTC.
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Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
43