FW82801EB Intel, FW82801EB Datasheet - Page 45

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Introduction
LAN Controller
The ICH5’s integrated LAN controller includes a 32-bit PCI controller that provides enhanced
scatter-gather bus mastering capabilities and enables the LAN controller to perform high speed
data transfers over the PCI bus. Its bus master capabilities enable the component to process high-
level commands and perform multiple operations; this lowers processor utilization by off-loading
communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help
prevent data underruns and overruns while waiting for bus accesses. This enables the integrated
LAN controller to transmit data with minimum interframe spacing (IFS).
The LAN controller can operate in either full duplex or half duplex mode. In full duplex mode the
LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half duplex
performance is enhanced by a proprietary collision reduction mechanism. See
Section 5.2
for
details.
RTC
The ICH5 contains a Motorola MC146818A-compatible real-time clock with 256 bytes of battery-
backed RAM. The real-time clock performs two key functions: keeping track of the time of day
and storing system data, even when the system is powered down. The RTC operates on a
32.768 KHz crystal and a separate 3 V lithium battery.
The RTC also supports two lockable memory ranges. By setting bits in the configuration space,
two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of
passwords or other system security information.
The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in
advance, rather than just 24 hours in advance.
GPIO
Various general purpose inputs and outputs are provided for custom system design. The number of
inputs and outputs varies depending on ICH5 configuration.
Enhanced Power Management
The ICH5’s power management functions include enhanced clock control, local and global
monitoring support for 14 individual devices, and various low-power (suspend) states
(e.g., Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management circuit
permits software-independent entrance to low-power states. The ICH5 contains full support for the
Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0b.
System Management Bus (SMBus 2.0)
The ICH5 contains an SMBus Host interface that allows the processor to communicate with
2
2
SMBus slaves. This interface is compatible with most I
C devices. Special I
C commands are
implemented.
The ICH5’s SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the ICH5 supports slave functionality,
including the Host Notify protocol. Hence, the host controller supports eight command protocols of
the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick
Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block
Read/Write, and Host Notify.
®
Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
45