FW82801EB Intel, FW82801EB Datasheet - Page 457

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

11.2.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
BMIC[P,S]—Bus Master IDE Command Register
(D31:F2)
Address Offset:
Default Value:
Bit
7:4
2:1
3
0
Reserved. Returns 0.
Read / Write Control (RWC) — R/W. This bit sets the direction of the bus master transfer: This bit
must NOT be changed when the bus master function is active.
0 = Memory reads
1 = Memory writes
Reserved. Returns 0.
Start/Stop Bus Master (START) — R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped
1 = Enables bus master operation of the controller. Bus master operation does not actually start
NOTE: This bit is intended to be cleared by software after the data transfer is completed, as
and then resumed. If this bit is reset while bus master operation is still active (i.e., the Bus
Master IDE Active bit of the Bus Master IDE Status register for that IDE channel is set) and the
drive has not yet finished its data transfer (the Interrupt bit in the Bus Master IDE Status register
for that IDE channel is not set), the bus master command is said to be aborted and data
transferred from the drive may be discarded instead of being written to system memory.
unless the Bus Master Enable bit (D31:F1: Offset 04h, bit 2) in PCI configuration space is also
set. Bus master operation begins when this bit is detected changing from 0 to 1. The controller
will transfer data between the IDE device and memory only when this bit is set. Master
operation can be halted by writing a 0 to this bit.
indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the Bus
Master IDE Status register for that IDE channel being set, or both. Hardware does not clear
this bit automatically.
Primary: 00h
Secondary: 08h
01h
Description
Attribute:
Size:
SATA Controller Registers (D31:F2)
R/W
8 bits
457