FW82801EB Intel, FW82801EB Datasheet - Page 469

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Bit
7
6
5
4
3
2
1
0
SMI at End of Pass-Through Enable (SMIATENDPS) — R/W. This bit enables SMI at the end of a
pass-through. This can occur if an SMI is generated in the middle of a pass-through, and needs to
be serviced later.
0 = Disable
1 = Enable
Pass Through State (PSTATE) — RO.
0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0.
1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.
A20Gate Pass-Through Enable (A20PASSEN) — R/W.
0 = Disable
1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence
SMI on USB IRQ Enable (USBSMIEN) — R/W.
0 = Disable
1 = Enable. USB interrupt will cause an SMI event.
SMI on Port 64 Writes Enable (64WEN) — R/W.
0 = Disable
1 = Enable. A 1 in bit 11 will cause an SMI event.
SMI on Port 64 Reads Enable (64REN) — R/W.
0 = Disable
1 = Enable. A 1 in bit 10 will cause an SMI event.
SMI on Port 60 Writes Enable (60WEN) — R/W.
0 = Disable
1 = Enable. A 1 in bit 9 will cause an SMI event.
SMI on Port 60 Reads Enable (60REN) — R/W.
0 = Disable
1 = Enable. A 1 in bit 8 will cause an SMI event.
involving writes to port 60h and 64h does not result in the setting of the SMI status bits.
Description
UHCI Controllers Registers
469