FW82801EB Intel, FW82801EB Datasheet - Page 470

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

UHCI Controllers Registers
12.1.17
12.2
470
Table 160. USB I/O Registers
USB_RES—USB Resume Enable Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
USB I/O Registers
Some of the read/write register bits that deal with changing the state of the USB hub ports function
such that on read back they reflect the current state of the port, and not necessarily the state of the
last write to the register. This allows the software to poll the state of the port and wait until it is in
the proper state before proceeding. A Host Controller Reset, Global Reset, or Port Reset will
immediately terminate a transfer on the affected ports and disable the port. This affects the
USBCMD register, bit 4 and the PORTSC registers, bits [12,6,2]. See individual bit descriptions
for more detail.
NOTES:
1. These registers are WORD writable only. Byte writes to these registers have unpredictable effects.
0D–0F
Offset
08–0B
00–01
02–03
04–05
06–07
10–11
12–13
14–17
Bit
7:2
1
0
18h
0C
Reserved
PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.
PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.
FRBASEADD
LOOPDATA
Mnemonic
PORTSC0
PORTSC1
USBCMD
USBINTR
SOFMOD
USBSTS
FRNUM
—
—
C4h
00h
USB Command
USB Status
USB Interrupt Enable
Frame Number
Frame List Base Address
Start of Frame Modify
Reserved
Port 0 Status/Control
Port 1 Status/Control
Reserved
Loop Back Test Data
Register Name
Description
Intel
®
Attribute:
Size:
82801EB ICH5 / 82801ER ICH5R Datasheet
Undefined
Default
0000h
0020h
0000h
0000h
0080h
0080h
40h
00h
—
—
R/W
8 bits
R/W (see Note 1)
R/WC, RO, R/W
R/WC, RO, R/W
(see Note 1)
(see Note 1)
R/WC
Type
R/W
R/W
R/W
R/W
RO
—
—