FW82801EB Intel, FW82801EB Datasheet - Page 474

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

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UHCI Controllers Registers
12.2.2
474
USBSTS—USB Status Register
I/O Offset:
Default Value:
This register indicates pending interrupts and various states of the host controller. The status
resulting from a transaction on the serial bus is not indicated in this register.
15:6
Bit
5
4
3
2
1
0
Reserved
HCHalted — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller has stopped executing as a result of the Run/Stop bit being set to 0, either
Host Controller Process Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller has detected a fatal error. This indicates that the host controller suffered a
Host System Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = A serious error occurred during a host system access involving the host controller module. In a
Resume Detect (RSM_DET) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller received a “RESUME” signal from a USB device. This is only valid if the
USB Error Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Completion of a USB transaction resulted in an error condition (e.g., error counter underflow). If
USB Interrupt (USBINT) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The host controller sets this bit when the cause of an interrupt is a completion of a USB
by software or by the host controller hardware (debug mode or an internal error). Default.
consistency check failure while processing a Transfer Descriptor. An example of a consistency
check failure would be finding an illegal PID field while processing the packet header portion of
the TD. When this error occurs, the host controller clears the Run/Stop bit in the Command
register to prevent further schedule execution. A hardware interrupt is generated to the system.
PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI
Target Abort. When this error occurs, the host controller clears the Run/Stop bit in the
Command register to prevent further execution of the scheduled TDs. A hardware interrupt is
generated to the system.
Host controller is in a global suspend state (bit 3 of Command register = 1).
the TD on which the error interrupt occurred also had its IOC bit set, both this bit and Bit 0 are
set.
transaction whose Transfer Descriptor had its IOC bit set. Also set when a short packet is
detected (actual length field in TD is less than maximum length field in TD), and short packet
detection is enabled in that TD.
Base + (02
0020h
03h)
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC
16 bits

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