FW82801EB Intel, FW82801EB Datasheet - Page 477

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

12.2.7
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: For Function 0, this applies to ICH5 USB ports 0 and 1; for Function 1, this applies to ICH5 USB
PORTSC[0,1]—Port Status and Control Register
I/O Offset:
Default Value:
ports 2 and 3; for Function 2, this applies to ICH5 USB ports 4 and 5; and for Function 3, this
applies to ICH5 USB ports 6 and 7.
After a Power-up Reset, Global Reset, or Host Controller Reset, the initial conditions of a port are:
no device connected, Port disabled, and the bus line status is 00 (SE0).
15:13
Bit
12
10
11
9
8
7
6
Reserved — RO.
Suspend — R/W. This bit should not be written to a 1 if global suspend is active (bit 3=1 in the
USBCMD register). Bit 2 and bit 12 of this register define the hub states as follows:
When in suspend state, downstream propagation of data is blocked on this port, except for
single-ended 0 resets (global reset and port reset). The blocking occurs at the end of the current
transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the
port is sensitive to resume detection. Note that the bit status does not change until the port is
suspended and that there may be a delay in suspending a port if there is a transaction currently in
progress on the USB.
1 = Port in suspend state.
0 = Port not in suspend state.
NOTE: Normally, if a transaction is in progress when this bit is set, the port will be suspended when
Overcurrent Indicator — R/WC. Set by hardware.
0 = Software clears this bit by writing a 1 to it.
1 = Overcurrent pin has gone from inactive to active on this port.
Overcurrent Active — RO. This bit is set and cleared by hardware.
0 = Indicates that the overcurrent pin is inactive (high).
1 = Indicates that the overcurrent pin is active (low).
Port Reset — R/W.
0 = Port is not in Reset.
1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling.
Low Speed Device Attached (LS) — RO.
0 = Full speed device is attached.
1 = Low speed device is attached to this port.
Reserved — RO. Always read as 1.
Resume Detect (RSM_DET) — R/W. Software sets this bit to a 1 to drive resume signaling. The
host controller sets this bit to a 1 if a J-to-K transition is detected for at least 32 microseconds while
the port is in the Suspend state. The ICH5 will then reflect the K-state back onto the bus as long as
the bit remains a 1, and the port is still in the suspend state (bit 12,2 are ‘11’). Writing a 0 (from 1)
causes the port to send a low speed EOP. This bit will remain a 1 until the EOP has completed.
0 = No resume (K-state) detected/driven on port.
1 = Resume detected/driven on port.
Bits [12,2]
X0
01
11
the current transaction completes. However, in the case of a specific error condition (out
transaction with babble), the Intel
port.
Port 0/2/4/6: Base + (10
Port 1/3/5/7: Base + (12
0080h
Hub State
Disable
Suspend
Enable
–
–
11h)
13h)
®
Description
ICH5 may issue a start-of-frame, and then suspend the
Attribute: R/WC, RO,
Size:
UHCI Controllers Registers
R/W (Word writes only)
16 bits
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