FW82801EB Intel, FW82801EB Datasheet - Page 481

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

13.1.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCICMD—PCI Command Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = The function is capable of generating interrupts.
1 = The function can not generate its interrupt to the interrupt controller.
Note that the corresponding Interrupt Status bit is not affected by the interrupt enable.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W.
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host Controller
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — RO. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — R/W.
0 = Disables this functionality.
1 = Enables the Intel
Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory Space
registers.
0 = Disables this functionality.
1 = Enables accesses to the USB 2.0 registers. The Base Address register for USB 2.0 should be
I/O Space Enable (IOSE) — RO. Hardwired to 0.
receive a completion status other than “successful” for one of its DMA-initiated memory reads
on the hub interface (and subsequently on its internal interface).
programmed before this bit is set.
04
0400h
–
05h
®
ICH5 to act as a master on the PCI bus for USB transfers.
(
EHC) is capable of generating (internally) SERR# when it
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W, RO
16 bits
481