FW82801EB Intel, FW82801EB Datasheet - Page 486

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

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EHCI Controller Registers (D29:F7)
13.1.16
13.1.17
486
PWR_CAPID—PCI Power Management Capability ID
Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
Bit
7:0
Bit
7:0
Power Management Capability ID — RO. A value of 01h indicates that this is a PCI Power
Management capabilities field.
Next Item Pointer 1 Value — R/W (special). This register defaults to 58h, which indicates that the
next capability registers begin at configuration offset 58h. This register is writable when the
WRT_RDONLY bit is set. This allows BIOS to effectively hide the Debug Port capability registers, if
necessary. This register should only be written during system initialization before the plug-and-play
software has enabled any master-initiated traffic. Only values of 58h (Debug Port visible) and 00h
(Debug Port invisible) are expected to be programmed in this register.
50h
01h
51h
58h
Description
Intel
Description
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO
8 bits
R/W (special)
8 bits

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