FW82801EB Intel, FW82801EB Datasheet - Page 502

no-image

FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FW82801EB
Manufacturer:
INTEL
Quantity:
20 000
Part Number:
FW82801EB SL73Z
Manufacturer:
INTEL
Quantity:
238
Part Number:
FW82801EB(SL73Z)
Manufacturer:
INTEL
Quantity:
20 000
EHCI Controller Registers (D29:F7)
13.2.6
502
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has no effect.
USB2.0_STS—USB 2.0 Status Register
Offset:
Default Value:
This register indicates pending interrupts and various states of the Host Controller. The status
resulting from a transaction on the serial bus is not indicated in this register. See the Interrupts
description in section 4 of the Enhanced Host Controller Interface Specification for Universal
Serial Bus, Revision 1.0 for additional information concerning USB 2.0 interrupt conditions.
31:16
11:6
Bit
15
14
13
12
5
4
Reserved. These bits are reserved and should be set to 0 when writing this register.
Asynchronous Schedule Status  RO. This bit reports the current real status of the Asynchronous
Schedule.
0 = Status of the Asynchronous Schedule is disabled. (Default)
1 = Status of the Asynchronous Schedule is enabled.
NOTE: The Host Controller is not required to immediately disable or enable the Asynchronous
Periodic Schedule Status  RO. This bit reports the current real status of the Periodic Schedule.
0 = Status of the Periodic Schedule is disabled. (Default)
1 = Status of the Periodic Schedule is enabled.
NOTE: The Host Controller is not required to immediately disable or enable the Periodic Schedule
Reclamation  RO. 0=Default. This read-only status bit is used to detect an empty asynchronous
schedule. The operational model and valid transitions for this bit are described in Section 4 of the
Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0.
HCHalted  RO.
0 = This bit is a 0 when the Run/Stop bit is a 1.
1 = The Host Controller sets this bit to 1 after it has stopped executing as a result of the Run/Stop bit
Reserved
Interrupt on Async Advance — R/WC. 0=Default. System software can force the host controller to
issue an interrupt the next time the host controller advances the asynchronous schedule by writing a
1 to the Interrupt on Async Advance Doorbell bit in the USB2.0_CMD register. This bit indicates the
assertion of that interrupt source.
Host System Error — R/WC.
0 = No serious error occurred during a host system access involving the Host Controller module
1 = The Host Controller sets this bit to 1 when a serious error occurs during a host system access
being set to 0, either by software or by the Host Controller hardware (e.g., internal error).
(Default)
involving the Host Controller module. A hardware interrupt is generated to the system. Memory
read cycles initiated by the EHC that receive any status other than Successful will result in this
bit being set.
When this error occurs, the Host Controller clears the Run/Stop bit in the USB2.0_CMDregister
to prevent further execution of the scheduled TDs. A hardware interrupt is generated to the
system (if enabled in the Interrupt Enable Register).
Schedule when software transitions the Asynchronous Schedule Enable bit in the
USB2.0_CMD register. When this bit and the Asynchronous Schedule Enable bit are the
same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
when software transitions the Periodic Schedule Enable bit in the USB2.0_CMD register.
When this bit and the Periodic Schedule Enable bit are the same value, the Periodic
Schedule is either enabled (1) or disabled (0).
CAPLENGTH + 04
00001000h
07h
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC, RO
32 bits

Related parts for FW82801EB